//******************************************************************/
//版本说明:
//V0.1		2017-03-30	11:00	yshao	复制自SL909_G01_X32
//******************************************************************/
`timescale	1ps/1ps
module SL909_G03(
                input	wire		sclkin,
                inout   tri             key_in,
                
                output  wire            JP202_PIN3,
                output  wire            JP202_PIN4,
		output	wire		JP202_PIN5,
                input	wire            JP202_PIN6,

		output	wire		sa_clk,
		output	wire	[2:0]	sa_cnt,
		output	wire		sa_dqm_l,
		output	wire		sa_dqm_h,
		output	wire	[10:0]	sa_addr,
                output	wire	[1:0]	sa_bank,
		inout	tri	[31:0]	sa_data,

		input	wire		mcu_dmx_tx,		//uart2_sync,
		output	reg		mcu_dmx_rx,		//uart3_sync,
		input	wire		mcu_dmx_ten,		//mcu_spi_sd,
		output	wire		mcu_dmx_ctrl,		//mcu_spi_miso,
		
		input	wire		mcu_spi_cs,
		input	wire		mcu_spi_clk,
		input	wire		mcu_spi_mosi,

		output	wire		spi2_cs,
		output	wire		spi2_clk,
		output	wire		spi2_mosi,
								
		output	wire		sd_clk,
		inout	tri		sd_cmd_sdi,
		input	wire		sd_dat0_sdo,
		input	wire		sd_dat1,
		input	wire		sd_dat2,
		inout	tri		sd_dat3_cs,
		input	wire		sd_cd,
		input	wire		sd_wp,

		input	wire		gp0_rxc,
		input	wire		gp0_rxdv,
		input	wire	[3:0]	gp0_rxd,
		output	wire		gp0_txc,
		output	wire		gp0_txen,
		output	wire	[3:0]	gp0_txd,
		
		input	wire		gp1_rxc,
		input	wire		gp1_rxdv,
		input	wire	[3:0]	gp1_rxd,
		output	wire		gp1_txc,
		output	wire		gp1_txen,
		output	wire	[3:0]	gp1_txd,

		output	wire	[7:0]	port_da,
		output	wire	[7:0]	port_le,
		input	wire	[7:0]	port_ex,
		
		input	wire	[7:0]	port_in,
		
		inout	tri		led_g
		);

//****************************************************************
//		内部信号
//****************************************************************
wire		resetb,oclk,clk_150M,sclk;
wire		pll_reset;
wire		time_1ms,time_125ms,time_250ms;
wire		time_1ms_sync,time_16us_sync,time_15ms_sync,time_250ms_sync,time_1s_sync;
wire		t_us,t_ms,t_s;

wire		rec_flag,rec_error,rec_error_sync,send_flag,pre_flag;
wire	[7:0]	rec_data,send_data;
wire	[1:0]	rec_vendor;
wire		yt_vs_pre,input_active,redu_flag,blank_flag;
wire	[7:0]	phy_state;

wire		op_start_flag,fpga_rec_flag,fpga_send_flag;
wire	[31:0]	op_start_addr;
wire	[7:0]	rec_buf_rdata;

wire		init_mode,init_end,reboot_en_fpga,reboot_en,comm_en;
wire		flash_op_ack,display_op_ack;
wire		flash_rec_end,flash_send_end,display_rec_end,display_send_end;
wire		flash_buf_we,display_buf_we;
wire	[7:0]	flash_buf_raddr,flash_buf_waddr,flash_buf_wdata;
wire	[7:0]	display_buf_raddr,display_buf_waddr,display_buf_wdata;
wire		read_start,read_end,read_d_ok,set_d_ok,ext_d_ok;
wire	[15:0]	set_addr,ext_addr;
wire	[23:0]	start_addr;
wire	[7:0]	read_data,set_data;
wire	[7:0]	state_data;

reg		vs,ds,h_start;
reg	[7:0]	data;
reg	[10:0]	h_num;
wire    [10:0]  h_total,l_total;
wire		vs_a,ds_a,v_start_a,h_start_a;
wire	[7:0]	data_a,state,state_2;
wire	[10:0]	h_num_a;
wire	[63:0]	unit_color_adj;

wire		v_start;

wire		black_mark;

wire		local_depth_en,cas_depth_adj;
wire	[7:0]   local_depth;

wire		flash_ms;
wire	[7:0]	no_vs_set;
reg		black_flag;

wire		shift_sync,display_sync,force_sync,more_adj_flag;
wire	[12:0]	shift_cycle_adj;

wire		r_frame_sync;

//added by yluo@2010-12-1
wire		init_correct_d_ok;
wire	[18:0]	init_correct_addr;
wire	[7:0]   init_correct_data;
wire            load_picture_flag,load_adj_flag;
reg	[10:0]	key_reboot_count;

wire            local_test_en,local_picture_en;
wire		press_detect;
wire            key_input;
wire            black;

wire		flash_SO;      
wire		flash_SCK;     
wire		flash_SI;
wire		flash_CS_n;
wire		clk_ok_n;
reg		clk_ok_n_t;
wire		tx_err_en;

wire            inner_led_g;

//DMX ACK
wire	[7:0]	dmx_ack_in;

wire	[9:0]	div_count_max;
wire	[2:0]	err_port_num;
wire		err_read_start;
wire	[3:0]	mem_active_port;//0：所有端口都选通，1~8，实际对应的1~8端口
wire		mem_read_start;

wire		chip_dmx_ack;

/////////mcu-fpga/////////////////////
wire		spi_rec_flag;
wire	[7:0]	spi_rec_data;
wire		spi_rec_error;
wire	[1:0]	spi_rec_vendor;

wire		spi_send_flag;
wire		spi_send_pre;
wire	[7:0]	spi_send_data;

wire		port_ctrl_req;
wire	[2:0]	port_sel;

//////////////////////////////////////
wire		vs_out;
wire	[1:0]	color_restore_type;
wire	[7:0]	led_light;
wire	[7:0]	testmode;

wire		nomal_driver,dect_in,dect_out;

//DMX输出信号
wire	[1:0]	dmx_mode;
wire	[2:0]	waddr_mode;
wire		dmx_rec_en;
wire	[7:0]	out_data_dmx, waddr_data;
reg	[7:0]	out_data_dmx_a, dmx_rec_enb;

//调试用信号
wire	[7:0]	disp_tout,m_tout;
wire	[31:0]	out_tout,dect_tout,ack_tout,sa_tout;
wire	[13:0]	dis_p_count;
//******************************************************************/
//			   参数定义
//******************************************************************/
//常数定义
parameter	SUB	=0;	   //分控
parameter	ASSIST	=1;	   //附属设备

parameter	ACTIVE	=1;
parameter	TEST	=2;	   
parameter	INIT	=3; 

parameter	INIT_ADDR	=14'b0000_0000_1100_00;//0x00C0_0000~0x00C3_FFFF
parameter	TEST_ADDR	=14'b0000_0000_1100_01;//0x00C4_0000~0x00C7_FFFF
parameter	ACT_ADDR	=14'b0000_0000_1100_10;//0x00C8_0000~0x00CB_FFFF

//仿真模式
parameter	Sim_Mode	=0;

//程序版本信息
parameter	MAIN_FUNCTION	=  "S";		//ASCII "S"  
parameter	SUB_FUNCTION	=  "L";		//ASCII "L"  
parameter	MAIN_FSOLUTION	=  9;		//"9"        
parameter	SUB_SOLUTION	=  9;		//"09"       
parameter	APPLICATION_TYPE=  "G";		//ASCII "G"  
parameter	MAIN_VERSION	=  8'd3;	//"03"       
parameter	SUB_VERSION	=  8'd5;	//"X01"  
parameter	MINI_VERSION	=  8'd6;	//" "  


//模块参数设置
defparam	out_ctrl_lamp.Sim_Mode 	= Sim_Mode;
defparam	sdram_top.Sim_Mode	= Sim_Mode;

defparam        phy_interface.DEVICE_TYPE   	=SUB;

defparam	reboot_ctrl.LOGIC_MODE		=ACTIVE;

defparam        com_ctrl.DEVICE_TYPE     	=SUB; 
defparam	com_ctrl.INITIAL_ADDR		=INIT_ADDR;
defparam 	com_ctrl.TEST_ADDR		=TEST_ADDR;
defparam  	com_ctrl.ACTIVE_ADDR		=ACT_ADDR;

defparam        state_ctrl.main_function   	=MAIN_FUNCTION;
defparam        state_ctrl.sub_function    	=SUB_FUNCTION;
defparam        state_ctrl.main_solution   	=MAIN_FSOLUTION;
defparam        state_ctrl.sub_solution    	=SUB_SOLUTION;
defparam        state_ctrl.application_type	=APPLICATION_TYPE;
defparam        state_ctrl.main_version    	=MAIN_VERSION;
defparam        state_ctrl.sub_version     	=SUB_VERSION;
defparam        state_ctrl.mini_version    	=MINI_VERSION;
//**************************************************************
//		时钟复位管理单元
//**************************************************************
//in            sclkin,sys_resetb
//out           sclk,tclk,oclk,resetb      

//out           time_1ms_sync,time_1ms

//上电后resetb保持0.1秒低电平
sys_reset_ctrl sys_reset_ctrl(
        .sclkin(sclkin),
        .resetb(resetb),
        .reset_phy()
        );

//PLL模块，输入25M时钟，产生125M和25M时钟
clk_gen	clk_gen_inst (
	.inclk0(sclkin),
	.c0(sclk),
	.c1(clk_25M),
	.locked(locked)
	);
	
//PLL模块，输入125M时钟，产生150M和输出给SDRAM的125M时钟
clk_gen2 clk_gen_inst_2 (
	.areset(pll_reset),
	.inclk0(sclk),
	.c0(clk_150M),
	.c1(sa_clk),
	.locked()
	);

//输出模块的工作时钟
assign	oclk=(Sim_Mode==0)?clk_150M:sclk;

//***************通讯测试**************
//用125M时钟检测PLL150M时钟
test_clk test_clk(
	.sclk(sclk),
	.clkin(clk_150M),
	.clk_ok_n(clk_ok_n)
	);

//输出模块的工作时钟
detect_pll_unlock detect_pll_unlock(
	.sclk(sclk),
	.resetb(resetb),
	.key_input(key_input),
	.clk_ok_n(clk_ok_n),
	.tx_err_en(tx_err_en),
	.time_1ms_sync(time_1ms_sync),
	.init_end(init_end),
	.pll_reset(pll_reset)
);

sys_timer       sys_timer(
                .resetb(resetb),
                .sclk(sclk),
                
                .time_1us(t_us),
                .time_1ms(time_1ms),
                .time_125ms(time_125ms),
                .time_250ms(time_250ms),
                .time_1s(t_s),
                
                .time_1ms_sync(time_1ms_sync),
                .time_16us_sync(time_16us_sync),
                .time_15ms_sync(time_15ms_sync),
                .time_125ms_sync(time_125ms_sync),
                .time_250ms_sync(time_250ms_sync),
                .time_1s_sync(time_1s_sync)   
                );
                
assign	t_ms = time_1ms;
                
//**************************************************************
//			整体控制
//**************************************************************
//in            init_end,fpga_rec_flag,op_start_flag,op_start_addr,
//out           init_mode,reboot_en,comm_en

//in            reboot_en

//in            rec_flag,rec_error;
//out           resetb,led_g,led_r,flash_ms,time_1ms  

//分控整体状态控制
s8_main_ctrl_01 main_ctrl(
		.resetb(resetb),
		.sclk(sclk),
		
		.init_end(init_end),
	        .input_active(1'b1),
		.key_active(1'b0),

		.ext_d_ok(ext_d_ok),
		.ext_addr(ext_addr),
		
		//模式控制
	        .init_mode(init_mode),
//	        .test_mode(),
		.reboot_en(reboot_en_fpga),
		.comm_en(comm_en),

		.tout(m_tout)
		);
		
wire	[23:0]	reboot_addr;
reboot_ctrl reboot_ctrl(
		.sclk(sclk),
		.resetb(resetb),
		
	        .cmd_d_ok(1'b0),
	        .cmd_addr(0),
	        .cmd_data(0),
	        
		.reboot_en_fpga(reboot_en_fpga),
		.reboot_addr(reboot_addr),
		.reboot_en(reboot_en)
	);
	
remote_sys remote_sys(
        .sclk(sclk),
        .reboot_en(reboot_en)
);

//led状态指示
Led_Ctrl_SV2	Led_Ctrl_SV2(
		.resetb(resetb),
		.sclk(sclk),
		
		.time_ms(time_1ms),
                .time_250ms(time_250ms),

		.G_black(0),
		.G_flash(rec_flag),//(testmode_ini_err&rec_flag),

		.R_light(black_mark),
		.R_flash(rec_error_sync),

		.G_flash_1st(1'd1),
		.R_flash_1st(1'd0),
		
		.tx_err_en(tx_err_en),
		
		.nG_led(inner_led_g),
		.nR_led()
		);

//***********LED灯和按键接口选通*************
ledG_press_IO ledG_press_IO(
                .sclk(sclk),
                .input_active(input_active),
                .detect_sync(time_15ms_sync),
                .sample_sync(time_1ms_sync),
                
                .inner_led_g(inner_led_g),
                .led_g(led_g),
                .key_in(key_in),
                .press(key_input)                
                );

//***********按键检测*************
button_debounce button(
		.resetb(resetb),
		.sclk(sclk),
		.a_second(time_250ms_sync),
		
		//按键输入
		.press(key_input),
		
		//按键确认输出
		.press_detect(press_detect)
		);
		
//**************************************************************
//		   千兆级联模块
//**************************************************************    
wire		rec_flag_a, rec_error_a, send_flag_a, pre_flag_a;
wire	[7:0]	rec_data_a, send_data_a;                

phy_interface phy_interface(
                .resetb(resetb),
                .sclk(sclk),
                .clk_25M(clk_25M),
                
		.cas_depth_adj(cas_depth_adj),
		.local_depth(local_depth),

		.tx_err_en(tx_err_en),
		.time_1ms(time_1ms),
		.time_125ms(time_125ms),	

		.gp0_rxc(gp0_rxc),
		.gp0_rxdv(gp0_rxdv),
		.gp0_rxd(gp0_rxd),
		.gp0_txc(gp0_txc),
		.gp0_txen(gp0_txen),
		.gp0_txd(gp0_txd),
		
		.gp1_rxc(gp1_rxc),
		.gp1_rxdv(gp1_rxdv),
		.gp1_rxd(gp1_rxd),
		.gp1_txc(gp1_txc),
		.gp1_txen(gp1_txen),
		.gp1_txd(gp1_txd),
		
		.rec_flag(rec_flag),
		.rec_data(rec_data),
		.rec_error(rec_error),
		.rec_error_sync(rec_error_sync),
		
		.send_flag(send_flag),
		.pre_flag(pre_flag),
		.send_data(send_data),

		.rec_vendor(rec_vendor),
		.yt_vs_pre(yt_vs_pre),
		.input_active(input_active),
		.redu_flag(redu_flag),
		.blank_flag(blank_flag),
		.phy_state(phy_state),
		
		.rec_flag_a(rec_flag_a),
		.rec_data_a(rec_data_a),
		.rec_error_a(rec_error_a),

		.send_flag_a(send_flag_a),
		.pre_flag_a(pre_flag_a),
		.send_data_a(send_data_a),

		.tout()
		);

//**************************************************************
//		通讯数据处理/上电初始化
//**************************************************************        
//in    rec_flag、rec_data、rec_error
//out   send_flag、pre_flag、send_data       
//out   set_d_ok、set_addr、set_data
//out   init_correct_d_ok、init_correct_addr、init_correct_data
//out   init_mode、init_end

//in/out   FLASH接口

//in    comm_en,init_mode
//out   init_end

reg		vs_b;
wire		ds_b, h_start_b;
wire	[7:0]	data_b;
wire	[2:0]	h_num_b;
wire	[7:0]	current_depth;
wire	[23:0]	local_net;
wire		local_net_en,l2048_mode,artnet_flag;
reg		artnet_mode;
wire	[7:0]	l9_com_tout;

L9_com_ctrl_02 com_ctrl_b(
		.resetb(resetb),
		.sclk(sclk),
		.comm_en(comm_en),

		.current_depth(current_depth),
		.local_net(local_net),
       		.local_net_en(local_net_en),
		
		.rec_flag(rec_flag_a),
		.rec_data(rec_data_a),
		.rec_error(rec_error_a),
		
		.send_flag(send_flag_a),
		.pre_flag(pre_flag_a),
		.send_data(send_data_a),
		
		.blank_flag(blank_flag),
		.redu_flag(redu_flag),
		.time_1ms_sync(time_1ms_sync),
		
		.mcu_spi_cs(mcu_spi_cs),
		.mcu_spi_clk(mcu_spi_clk),
		.mcu_spi_mosi(mcu_spi_mosi),
		
		.spi2_cs(spi2_cs),
		.spi2_clk(spi2_clk),
		.spi2_mosi(spi2_mosi),
		
		.port_ctrl_req(port_ctrl_req),
		.port_sel(port_sel),

		.artnet_flag(artnet_flag),
		.dsout(ds_b),
		.dout(data_b),
		.h_start(h_start_b),
		.h_num(h_num_b),
		.l2048_mode(),
		
		.tout(l9_com_tout)
		);

v8_com_ctrl_01 com_ctrl(
		.resetb(resetb),
		.sclk(sclk),
		.comm_en(comm_en),

		.local_depth_en(local_depth_en),
		.local_depth(local_depth),
		.current_depth(current_depth),

		.rec_flag(rec_flag),
		.rec_error(rec_error),
		.rec_data(rec_data),
		.rec_vendor(rec_vendor),
		
		.send_flag(send_flag),
		.pre_flag(pre_flag),
		.send_data(send_data),
		
		.blank_flag(blank_flag),
		.redu_flag(redu_flag),
		.time_1ms_sync(time_1ms_sync),
		
		.fpga_rec_flag(fpga_rec_flag),
		.fpga_send_flag(fpga_send_flag),
		.op_start_flag(op_start_flag),
		.op_start_addr(op_start_addr),
		.op_length(),
		.op_ack(flash_op_ack | display_op_ack),

		.fpga_rec_end(flash_rec_end | display_rec_end),	
		.rec_buf_raddr(flash_buf_raddr | display_buf_raddr),
		.rec_buf_rdata(rec_buf_rdata),		

		.fpga_send_end(flash_send_end | display_send_end),	
		.send_buf_we(flash_buf_we | display_buf_we),
		.send_buf_waddr(flash_buf_waddr | display_buf_waddr),
		.send_buf_wdata(flash_buf_wdata | display_buf_wdata),	
		
		.tout()
		);


//flash控制  
v8_flash_ctrl_02 flash_ctrl(
		.resetb(resetb),
		.sclk(sclk),

		//和通讯模块接口
		.fpga_rec_flag(fpga_rec_flag),
		.fpga_send_flag(fpga_send_flag),
		.op_start_flag(op_start_flag),
		.op_start_addr(op_start_addr),
		.op_length(8'hFF),
		.op_ack(flash_op_ack),

		.rec_end(flash_rec_end),
		.rec_buf_raddr(flash_buf_raddr),
		.rec_buf_rdata(rec_buf_rdata),		

		.send_end(flash_send_end),
		.send_buf_we(flash_buf_we),
		.send_buf_waddr(flash_buf_waddr),
		.send_buf_wdata(flash_buf_wdata),	

		//和显示模块接口
		.read_start(read_start),
		.start_addr(start_addr),
		.read_end(read_end),
                		
		.read_d_ok(read_d_ok),
		.read_data(read_data),

		//和flash接口
	        .flash_SO(flash_SO),
		.flash_SCK(flash_SCK),
		.flash_SI(flash_SI),
		.flash_CS_n(flash_CS_n),

        	.tout()
		);

epcs_io epcs_io(
	.asdo_in(flash_SI),
	.asmi_access_granted(1'b1),
	.dclk_in(flash_SCK),
	.ncso_in(flash_CS_n),
	.noe_in(1'b0),
	.asmi_access_request(),
	.data0_out(flash_SO));
                    
//显示设置接口
display_bus_01 display_bus(
		//复位，时钟，工作使能
		.resetb(resetb),
		.sclk(sclk),
		.init_mode(init_mode),
		.init_end(init_end),
                
                //模式配置
                .cc_128_16(1'b0), 
                .cc_256_16(1'b0),
		
		//和通讯控制模块接口
		.fpga_rec_flag(fpga_rec_flag),
		.fpga_send_flag(fpga_send_flag),
		.op_start_flag(op_start_flag),
		.op_start_addr(op_start_addr),
		.op_length(8'hFF),
		.op_ack(display_op_ack),

		.rec_end(display_rec_end),
		.rec_buf_raddr(display_buf_raddr),
		.rec_buf_rdata(rec_buf_rdata),		

		.send_end(display_send_end),
		.send_buf_we(display_buf_we),
		.send_buf_waddr(display_buf_waddr),
		.send_buf_wdata(display_buf_wdata),	

		//和flash模块接口
		.read_start(read_start),
		.start_addr(start_addr),
		.read_end(read_end),
		
		.read_d_ok(read_d_ok),
		.read_data(read_data),

		//内部寄存器设置总线
	        .set_d_ok(set_d_ok),
	        .set_addr(set_addr),
	        .set_data(set_data),
		
	        .ext_d_ok(ext_d_ok),
	        .ext_addr(ext_addr),
	        
		//逐点调整数据设置总线
		.init_correct_d_ok(init_correct_d_ok),
	        .init_correct_addr(init_correct_addr),
	        .init_correct_data(init_correct_data),
	        .load_adj_flag(),
	        .load_picture_flag(),
	        
		//读取返回数据的接口
	       	.sys_state_data(state_data),
	       	.dmx_ack_data(8'h0),

                //调试信号接口
        	.tout(disp_tout)
		);

//系统状态数据生成
state_ctrl_02	state_ctrl(
		.resetb(resetb),
        	.sclk(sclk),

		//设置总线接口
		.fpga_rec_flag(fpga_rec_flag),
		.ext_addr(ext_addr),
		.set_addr(set_addr),
		.set_d_ok(set_d_ok),
		.set_data(set_data),
		
		//千兆PHY接口,包错误统计
		.rec_flag(rec_flag),
		.rec_error(rec_error),

		//状态寄存器
	       	.state_data(state_data),
		        
		//接口模块返回的状态数据
		.phy_state(phy_state),	

		//DMX模块返回的状态数据
		.dmx_state_data(8'h0),
		
		//调试用返回的状态数据
		.debug_data({cas_depth_adj,local_depth_en}),
		
		//输出给led灯和输出控制模块
		.black_mark(black_mark)
		);

//**************************************************************
//		  显示数据处理
//************************************************************** 
wire	[31:0]	rec_tout;

L9_data_rec_02 data_rec(
		.resetb(resetb),
		.sclk(sclk),
		
		//配置总线
	        .set_d_ok(set_d_ok),
	        .set_addr(set_addr),
	        .set_data(set_data),
	        
		//工作模式控制
		.init_mode(init_mode),
		.black(black),
		
		//开机渐亮控制
		.test_vs(0),
		.local_test_en(local_test_en),
		.local_picture_en(local_picture_en),        
		
		.local_net(local_net),
       		.local_net_en(local_net_en),

		//多模块共用设置数据输出
		.h_total(h_total),
                .l_total(l_total),
		.no_vs_set(no_vs_set),
		.local_depth(local_depth),
       		.cas_depth_adj(cas_depth_adj),
       		.local_depth_en(local_depth_en),
		
		//PHY模块接口
		.mac_flag(rec_flag),
		.mac_data(rec_data),
		.mac_error(rec_error),
		.mac_vendor(rec_vendor),
		
		//显示数据输出
		.vsout(vs_a),
		.dsout(ds_a),
		.dout(data_a),
		.h_start(h_start_a),
		.h_num(h_num_a),
		.l2048_mode(l2048_mode),
		
                //显示设置数据输出
		.state(state),	
		.state_2(state_2),
		.color_restore_type(color_restore_type),
		.testmode(testmode),
		.unit_color_adj(unit_color_adj),
                .cascade_light(),
		.led_light(led_light),

		//调试用信号输出
		.tout(rec_tout)
		);

//无信号时测试数据生成
test_out_01 test_out(
		.resetb(resetb),
		.sclk(sclk),
                
                //时间信号
		.frame_flag(time_15ms_sync),
		.a_second(time_1s_sync),
		
                //PHY有效标志和按键确认
		.input_active(input_active),
		.press_detect(press_detect),
		
 		//测试模式配置
		.no_vs_set(no_vs_set), 
		.pixel_mode(2'b00),
		.h_max(h_total),
                .l_max(l_total),
 		//虚拟效果使能
		.vir_disp(state[7]),
		
		//显示数据输入
		.vsin(0),
		.h_num_in(0),
		.hsin(0),
		.din(0),
		
		//显示数据输出
		.vsout(),		//多时钟帧信号
		.v_start(),	//单时钟帧信号
		.h_num_out(),
		.hsout(),
		.dout(),
		
		//显示数据输出模式
		.local_test_en(local_test_en),
		.local_picture_en(local_picture_en),
		
		//调试用信号输出
		.tout()
		);
	
//**************************************************************
//         显示数据存储与读取
//************************************************************** 
wire		disp_read_req;
wire	[23:0]	disp_read_addr;
wire	[3:0]	disp_read_cnt;
wire            disp_read_ack;
wire    [31:0]  disp_read_data;

wire 	[7:0]	out_data;
wire 	[7:0]	out_data_n;
wire            clk_out;
wire            clk_out_n;

reg	[5:0]	time_33ms_count;

always @(posedge sclk or negedge resetb)
	if (resetb == 0)
		artnet_mode <= 0;
	else if (artnet_flag == 1)
		artnet_mode <= 1;
	else if (vs_a == 1)
		artnet_mode <= 0;

always @(posedge sclk or negedge resetb)
	if (resetb == 0)
		time_33ms_count <= 0;
	else if (time_33ms_count[5] == 1)
		time_33ms_count <= 0;
	else if (time_1ms_sync == 1)
		time_33ms_count <= time_33ms_count + 1;

always @(posedge sclk)
	if (artnet_mode == 1 && time_33ms_count == 1 && time_1ms_sync == 1)
		vs_b <= 1;
	else
		vs_b <= 0;

always @(posedge sclk)
	vs <= vs_a | vs_b;
	
always @(posedge sclk)
	if (artnet_mode == 1) begin
		ds <= ds_b;
		h_num <= h_num_b;
		data <= data_b;
		h_start <= h_start_b;
	end
	else begin
		ds <= ds_a;
		h_num <= h_num_a;
		data <= data_a;
		h_start <= h_start_a;
	end

s8_sdram_top_01 sdram_top(
        .resetb(resetb),
        .sclk(sclk),

        .init_mode(init_mode),
        .set_addr(set_addr),	
	.set_data(set_data),
	.set_d_ok(set_d_ok),
	
        .sync_16_us(time_16us_sync),
        
	.vsin(vs),
	.dsin(ds),
	.din(data),
	.h_start(h_start),
	.h_num(h_num),
	.l2048_mode(l2048_mode),
	.artnet_mode(artnet_mode),
        
	.vs_out(vs_out),
	.state(state),

        .read_req (disp_read_req),
        .read_addr(disp_read_addr),
        .read_cnt(disp_read_cnt),
        .read_ack (disp_read_ack),
        .read_data(disp_read_data),

        .sa_clk(),
        .sa_cnt(sa_cnt),
        .sa_addr(sa_addr),
        .sa_bank(sa_bank),
        .sa_data(sa_data),
        
        .tout(sa_tout)
        );

assign        sa_dqm_l=0;
assign        sa_dqm_h=0;

//**************************************************************
//		        输出控制
//************************************************************** 
//in    input_active,no_vs_set,comm_en
//in    set_d_ok,set_addr,set_data
//

//out   显示输出接口

//黑屏控制
black_ctrl      black_ctrl(
                .resetb(resetb),
                .sclk(sclk),
                
                .time_125ms_sync(time_125ms_sync),
                .init_mode(init_mode),
                .input_active(input_active),
                .local_test_en(local_test_en),
                
                .black_mark(black_mark),                  
                .state(state), 
                .no_vs_set(no_vs_set),
                
                .black(black)
                );  

//灯饰输出控制模块
out_ctrl_lamp out_ctrl_lamp(
        .resetb			(resetb),
        .sclk			(sclk),
	.oclk			(oclk),
        
        .set_d_ok		(set_d_ok),
        .set_addr		(set_addr),
        .set_data		(set_data),
        
        .ext_d_ok		(ext_d_ok),
        .ext_addr		(ext_addr),

        .init_correct_d_ok	(init_correct_d_ok),
        .init_correct_addr	(init_correct_addr),
        .init_correct_data	(init_correct_data),
        
        .t_us			(t_us),
        .t_ms			(t_ms),
        .t_s			(t_s),

        .out_en			(comm_en),
        .v_start		(vs),
        .black			(black),
        .state			(state),
        .state_2		(state_2),
 //       .color_restore_type	(2'b00),
        .color_restore_type	(color_restore_type),
	.led_light		(led_light),
        
	.unit_color_adj		(unit_color_adj),

        .disp_read_req		(disp_read_req),
        .disp_read_addr		(disp_read_addr),
        .disp_read_cnt		(disp_read_cnt),
        .disp_read_ack		(disp_read_ack),
        .disp_read_data		(disp_read_data),
               
        .vs_out			(vs_out),
        
        .out_sync		(out_sync),
        .out_data		(out_data),
        .out_data_n		(out_data_n),
        .clk_out		(clk_out),
        .clk_out_n		(clk_out_n),

 	//DMX输出信号
	.dmx_mode		(dmx_mode),
        .dmx_rec_en		(dmx_rec_en),
        .out_data_dmx		(out_data_dmx),
  	//DMX写址信号
	.pin4_w_active		(pin4_w_active),
	.waddr_mode		(waddr_mode),
        .waddr_data		(waddr_data),

	.mem_err_sel		(),
        .err_port_num		(err_port_num),
        .err_read_start		(err_read_start),
        .div_count_max		(div_count_max),
        .mem_active_port	(mem_active_port),
        .mem_read_start		(mem_read_start),

        .tout			(out_tout)     
	);

//背板类型检测
/*
hub_detect hub_detect(
	.resetb(resetb),
	.sclk(sclk),

	.dect_out(dect_out),	
	.dect_in(dect_in),
		
	.nomal_driver(nomal_driver),	

	.tout(dect_tout)	
	);
		
*/
assign nomal_driver = 1;
				
//************************************************************/
//		单片机RDM控制
//************************************************************/
reg	[7:0]	port_mask;

assign	mcu_dmx_ctrl = port_ctrl_req;
	
always @(posedge sclk)
	if (mcu_dmx_ctrl == 0)
		port_mask <= 0;
	else
		case (port_sel)
			0:	port_mask <= 8'h01;
			1:	port_mask <= 8'h02;
			2:	port_mask <= 8'h04;
			3:	port_mask <= 8'h08;
			4:	port_mask <= 8'h10;
			5:	port_mask <= 8'h20;
			6:	port_mask <= 8'h40;
			7:	port_mask <= 8'h80;
			default:	port_mask <= 0;
		endcase
		

always @( * )
	out_data_dmx_a <= (out_data_dmx & (~port_mask)) | ({8{mcu_dmx_tx}} & port_mask);
	
always @( * )
	dmx_rec_enb <= ({8{~dmx_rec_en}} & (~port_mask)) | ({8{mcu_dmx_ten}} & port_mask);
	
	
always @( * )
	if (mcu_dmx_ctrl == 0)
		mcu_dmx_rx <= 1;
	else if (mcu_dmx_ten == 1)
		mcu_dmx_rx <= 1;
	else
		case (port_sel)
			0:	mcu_dmx_rx <= dmx_ack_in[0];
			1:	mcu_dmx_rx <= dmx_ack_in[1];
			2:	mcu_dmx_rx <= dmx_ack_in[2];
			3:	mcu_dmx_rx <= dmx_ack_in[3];
			4:	mcu_dmx_rx <= dmx_ack_in[4];
			5:	mcu_dmx_rx <= dmx_ack_in[5];
			6:	mcu_dmx_rx <= dmx_ack_in[6];
			7:	mcu_dmx_rx <= dmx_ack_in[7];
			default:	mcu_dmx_rx <= 1;
		endcase
		
//************************************************************/
//		背板接口
//************************************************************/
reg	[7:0]	port_da_d, port_le_d, port_ex_d;
reg		testmode_en;

//assign  port_da = {rec_flag_a,spi2_cs,spi2_clk,spi2_mosi,mcu_spi_cs,mcu_spi_clk,mcu_spi_mosi};//port_da_d;  
//assign  port_le = l9_com_tout;//port_le_d;  
assign  port_da = port_da_d;  
assign  port_le = port_le_d;  
//assign	port_ex[3:0] = (dmx_mode[1]==1)?{4'hz}:port_ex_d[3:0];
//assign	port_ex[4]   = 1'hz;
//assign	port_ex[7:5] = (dmx_mode[1]==1)?{3'hz}:port_ex_d[7:5];
//assign	port_ex[7:5] = {1'hz,dect_out,1'hz};

//返回dmx接收数据
assign	dmx_ack_in = port_ex[7:0];
assign	dect_in = port_ex[4];

wire	dect_ttt;
assign	dect_ttt = port_ex[7];
//***********************************************
//		输出信号
//***********************************************
always @(posedge sclk)
	if (testmode == 8'h3C)
		testmode_en <= 1;
	else
		testmode_en <= 0;

always @*
	case (dmx_mode)
		2'b01: begin	//普通DMX芯片
			if(nomal_driver == 1) begin	//SC1521D背板
				if (waddr_mode[0] == 1) begin		//TM512/UCS512A写址
					port_da_d <= 8'hFF;
					port_le_d <= 8'hFF;
					port_ex_d <= {1'b0,dect_out,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1};
					end
				else if (waddr_mode[2:1] != 0) begin	//TM512C/Sm1651X写址
					port_da_d <= waddr_data;
					port_le_d <= 8'hFF;
					port_ex_d <= {1'b0,dect_out,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1};
					end
				else begin
					port_da_d <= out_data_dmx_a;
					port_le_d <= dmx_rec_enb;
					port_ex_d <= 8'h0;
					end
				end
			else begin			//SC1521DW背板
				if (waddr_mode[0] == 1)	begin	//TM512/UCS512A写址
					port_da_d <= 8'hFF;
					if (pin4_w_active == 1)
						port_le_d <= {8{~waddr_data[0]}};
					else
						port_le_d <= waddr_data;
					if (pin4_w_active == 1)
						port_ex_d <= {1'b0,dect_out,1'b0,1'b0,1'b0,1'b0,waddr_data[0],1'b1};
					else
						port_ex_d <= {1'b0,dect_out,1'b0,1'b0,1'b0,1'b0,~waddr_data[0],1'b1};
					end
				else if (waddr_mode[2:1] != 0) begin	//TM512C/Sm1651X写址
					port_da_d <= waddr_data;
					port_le_d <= 1'b1;
					port_ex_d <= {1'b0,dect_out,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1};
					end
				else if (testmode_en == 1)begin		//测试SC1521DW背板
					port_da_d <= out_data_dmx_a;
					port_le_d <= {8{out_data_dmx[0]}};
					port_ex_d <= {1'b0,dect_out,1'b0,1'b0,1'b0,1'b0,~out_data_dmx,1'b1};
					end
				else begin				//正常工作
					port_da_d <= out_data_dmx_a;
					port_le_d <= 8'hFF;
					port_ex_d <= {1'b0,dect_out,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1};
					end
				end
			end
		2'b11: begin	//iColor DMX芯片
			if(nomal_driver == 1) begin	//SC1521D背板
				if (waddr_mode[0] == 1) begin		//TM512/UCS512A写址
					port_da_d <= 8'hFF;
					port_le_d <= 8'hFF;
					port_ex_d <= {1'b0,dect_out,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1};
					end
				else if (waddr_mode[2:1] != 0) begin	//TM512C/Sm1651X写址
					port_da_d <= waddr_data;
					port_le_d <= 8'hFF;
					port_ex_d <= {1'b0,dect_out,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1};
					end
				else begin
					port_da_d <= out_data_dmx_a;
					port_le_d <= dmx_rec_enb;
					port_ex_d <= 8'h0;
					end
				end
			else begin			//SC1521DW背板(该分支当前无法被选择）
				if (waddr_mode[0] == 1) begin		//TM512/UCS512A写址
					port_da_d <= 8'hFF;
					port_le_d <= waddr_data;
					port_ex_d <= {1'b0,dect_out,1'b0,1'b0,1'b0,1'b0,~waddr_data[0],1'b1};
					end
				else if (waddr_mode[2:1] != 0) begin	//TM512C/Sm1651X写址
					port_da_d <= waddr_data;
					port_le_d <= 1'b1;
					port_ex_d <= {1'b0,dect_out,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1};
					end
				else begin
					port_da_d <= out_data_dmx_a;
					port_le_d <= 8'hFF;
					port_ex_d <= {1'b0,dect_out,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1};
					end	
				end
			end
		default: begin	//串行芯片
			if(nomal_driver == 1) begin	//SC1521背板
				port_da_d <= out_data;
				port_le_d <= out_data_n;
				port_ex_d <= {1'b0,dect_out,1'b0,1'b0,1'b0,clk_out,clk_out_n,1'b1};
				end
			else begin			//SC1521DW背板
				port_da_d <= out_data;
				port_le_d <= {8{clk_out_n}};
				port_ex_d <= {1'b0,dect_out,1'b0,1'b0,1'b0,1'b0,clk_out,1'b1};
				end	
			end
	endcase
		
//************************************************************/
//		未用接口
//************************************************************/                    

//面板接口
//assign	JP202_PIN3 = gp0_rec_flag;
//assign	JP202_PIN4 = gp1_rec_flag;
//assign	JP202_PIN5 = input_active;

//assign  JP202_PIN3 = rec_flag;
//assign  JP202_PIN4 = set_d_ok;
//assign	JP202_PIN5 = out_tout[12];

//assign  JP202_PIN3 = out_tout[0];
//assign  JP202_PIN3 = out_tout[3] & (~ out_tout[13]);
//assign  JP202_PIN4 = out_tout[3] & out_tout[13];
//assign	JP202_PIN5 = out_tout[5];
//assign  JP202_PIN3 = out_tout[24];
//assign  JP202_PIN4 = out_tout[25];
//assign	JP202_PIN5 = set_d_ok;//out_tout[26];

//assign  JP202_PIN3 = vs;	//1'b0;
//assign  JP202_PIN4 = rec_flag;// & ack_tout[0];
//assign	JP202_PIN5 = hs;

//帧行信号输出		
//assign	JP202_PIN3 = vs_a;
//assign	JP202_PIN4 = hs_a;
//assign	JP202_PIN5 = state[2];
//assign	sd_clk = vs_out;

assign	JP202_PIN3 = vs_b;//dect_tout[0];//vs_b;
assign	JP202_PIN4 = artnet_mode;//dect_tout[1];//ds_b;
assign	JP202_PIN5 = time_33ms_count[4];//dect_ttt;//h_start_b;
assign	sd_clk = sa_tout[0];

//SD接口
//assign	sd_clk = 1'b0;
assign	sd_cmd_sdi = 1'bz;
assign	sd_dat3_cs = 1'bz;

assign	spi2_miso = vs_out;
//assign	mcu_spi_miso = 1'b0;

endmodule


